1. Field of the Invention
The present invention relates to a method of manufacturing a capacitor used for a memory cell of a semiconductor device, e.g., a dynamic RAM and, more particularly, to a method of forming a thin insulating film between polycrystalline silicon layers.
2. Description of the Related Art
Increases in the packing density of dynamic RAMs (to hereinafter be referred to as DRAMs) having a capacitor in each memory cell and storing data way of a stored by charge in the capacitor have resulted in the data stored each capacitor being liable to destruction by even small external charge. This problem is known as a soft error, and has resulted in the need for a sufficiently large memory cell capacitance to be provide in order to prevent its occurrence. One promising means of ensuring an adequate capacitance is to increase the capacitor area, and various methods of doing so have been proposed, among them, utilization of three-dimensional structures. For example, in one method, a groove is formed in the surface of a semiconductor substrate, whereby the substrate has a large surface region, which can serve as a capacitor region. In another method, a capacitor is stacked on a MOS transistor of each memory cell. In some capacitors obtained by these methods, a thin insulating film is formed between polycrystalline silicon layers.
As a material of the above insulating film, an insulating film obtained by depositing a silicon nitride film on polycrystalline silicon and oxidizing its surface is used, as is described in Y. OHJI et al. "RELIABILITY OF NANOMETER THICK MULTI-LAYER DIELECTRIC FILMS ON POLY-CRYSTALLINE SILICON", at 25th annual proceedings, Apr. 7, 8, and 9, 1987. By using this material, a highly reliable capacitor structure having a very thin insulating film and a high capacitance can be realized. A conventional method of manufacturing such a capacitor will now be described below.
A first oxide film is formed on a silicon semiconductor substrate by thermal oxidation or the like. Then, a first polycrystalline silicon layer doped with a high concentration of, for example, As or P is deposited on the first oxide film. At this stage, an undesired second oxide film is inevitably formed on the first polycrystalline silicon layer, for reasons which will be described hereinafter. A silicon nitride film is deposited on the second oxide film by low pressure CVD. The surface of the silicon nitride film is oxidized to form a third oxide film. A second polycrystalline silicon layer is then deposited on the third oxide film. With this process, a capacitor is formed between the first and second polycrystalline silicon layers.
In the manufacture of the above-described capacitor, since an impurity of a high concentration is diffused in a first polycrystalline silicon layer as a lower layer, when this first polycrystalline silicon layer is formed, a natural oxide film tends to be formed on its surface. In this case, a natural oxide film having a thickness of 5 to 10 .ANG. is formed at a room temperature. Thereafter, a silicon nitride film is deposited on the first polycrystalline silicon layer by low pressure CVD. Since a low pressure CVD furnace is normally set at 600.degree. C. or more, the natural oxide film on the first polycrystalline silicon layer is further grown, and its thickness often reaches 20 to 30 .ANG..
That is, the thickness of the insulating film between the first and second polycrystalline silicon layers is excessively increased due to the second oxide film formed on the first polycrystalline silicon layer by natural oxidation. As a result, the capacitance is decreased. Since the thickness of the second oxide film is changed depending on the concentration of an impurity contained in the first polycrystalline silicon layer and an ambient temperature, film thickness controllability of the capacity is considerably degraded. In addition, electrons are trapped at an interface between the second oxide film and the silicon nitride film formed subsequently, the characteristics of a capacitor vary, and hence a defective memory cell not having a predetermined capacitance may be manufactured.